|
General information
|
|
Type
|
CPU / Microprocessor
|
|
Market segment
|
Desktop
|
|
Family
|
Intel Pentium MMX
|
|
CPU part number
|
-
BP80503200 is an OEM/tray microprocessor
|
|
Frequency
|
200 MHz
|
|
Bus speed
|
66 MHz
|
|
Clock multiplier
|
3
|
|
Package
|
296-pin Staggered Plastic Pin Grid Array (PPGA)
296-pin Ceramic Staggered Pin Grid Array (SPGA)
1.95" x 1.95" (4.95 cm x 4.95 cm)
|
|
Socket
|
Socket 7
|
|
Introduction date
|
8-Jan-97
|
|
Price at introduction
|
$550
|
|
S-spec numbers
|
|
Part number
|
Production processors
|
|
|
SL23S
|
SL23W
|
SL25N
|
SL26Q
|
SL274
|
SL28J
|
SL2FQ
|
SL2S9
|
|
BP80503200
|
+
|
+
|
+
|
+
|
+
|
+
|
+
|
+
|
|
|
Architecture / Microarchitecture
|
|
Microarchitecture
|
P5
|
|
Processor core
|
P55C
|
|
Core steppings
|
xA3 (SL23S, SL25N, SL26Q, SL274)
xB1 (SL23W, SL2FQ, SL2S9)
|
|
CPUIDs
|
543 (SL23W, SL2FQ, SL2S9)
544 (SL23S, SL25N, SL26Q, SL274)
2543 (SL23W, SL2FQ, SL2S9)
2544 (SL23S, SL25N, SL26Q, SL274)
|
|
Manufacturing process
|
0.35 micron CMOS process, 4.5 million transistors
|
|
Data width
|
32 bit
|
|
Data bus width
|
64 bit
|
|
Floating Point Unit
|
Integrated
|
|
Level 1 cache size
|
16 KB 4-way set associative code cache
16 KB 4-way set associative write-back data cache
|
|
Physical memory
|
4 GB
|
|
Multiprocessing
|
Up to 2 processors
|
|
Features
|
MMX instructions
|
|
Low power features
|
-
System Management Mode
-
Clock Control
-
SL power-management features
|
|
On-chip peripherals
|
-
Memory Management Unit
-
Local Advanced Programmable Interrupt Controller
|
|
Electrical / Thermal parameters
|
|
Min/Recommended/Max V core
|
2.7V / 2.8V / 2.9V
|
|
Min/Recommended/Max V I/O or secondary
|
3.135V / 3.3V / 3.6V
|
|
Minimum/Maximum operating temperature
|
0°C - 70°C
|
|
Minimum/Typical/Maximum power dissipation
|
2.41 Watt (Stop Grant mode) / 7.3 Watt / 18.87 Watt
|
|
Thermal Design Power
|
15.7 Watt
|
|
Notes on Intel Pentium MMX 200 MHz
|
-
Minimum bus frequency is 33 MHz
|
